Torching semiconductors for fun and profit

Det3 Labs VHDL Hub

VHDL is the primary language we use to develop synthesizable digital circuits, and as such we felt it would be cool to provide data on what tools we use, how our build environment is set up, and some VHDL modules that you might find useful in your own designs.

Build Tools and Intro

Our primary simulation and test system uses Mentor Graphics' ModelSim, but we prefer to keep things open by using a standard UNIX build environment. For those of us still running Windows, we run a UNIX layer called Cygwin, which provides everything we need. While Det3 tries to be editor-neutral, many of us prefer using GNU Emacs for our primary editor, with the help of the wonderful Emacs VHDL Mode add-in by Reto Zimmerman. The VHDL mode provides many useful bits such as syntax highlighting, templating, block commenting, and a module heirarchy browser.

Our build system is controlled by make, and calls the command-line versions of the ModelSim tools. For larger projects, such as custom programmable DSPs and MCUs, we use a host of other tools such as PERL, GCC, GNU Bison, and GNU flex. The UNIX environment provides many additional tools we may or may not use on a project-by-project basis.

For synthesis, we choose to stick with the standard Xilinx WebPack, Altera Quartus, and Lattice ispLEVER tools since they have a wide install-base, and provide a minimum investment cost for clients that wish to use source code we develop. For more complex designs, we also use synthesis tools from Synplicity Corporation to accelerate completion of designs.

Code Structure

We have many goals when writing VHDL code. Among these are readability, being able to clearly partition synthesizable code from equivalent simulation models, and code reuse. One thing we feel is unique to our coding style is the structure for each project we have. While it is slightly more verbose, it allows us to quickly retarget designs for different FPGAs as well as migrating from an FPGA to more traditional ASIC paths.

Our design hierarchy starts with the synthesis top-level, which is only a wrapper. We require every signal at this level to be a scalar signal, and that no logic is contained in this level. The purpose of the synthesis top-level is to apply architecture specific constraints to the design, such as timing and signal-to-pin mapping. Signals feed from this entity down to the simulation top-level.

The simulation top-level is the main entity within the design. This is where all bidirectional signals (such as data busses) get split into separate input and output buffers. No bidirectional signals are allowed beneath this level. This provides a solid top-level design to perform simulation on, using either RTL or abstract modeled VHDL.

Below these two top-levels, we have the specific logic blocks that perform detailed functions, and they are outside of the scope of this introduction. We'll be publishing Det3 VHDL coding guidelines in the near future.

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