Detachment 3 Laboratories
Torching semiconductors for fun and profit
This is a collection of fairly useful VHDL code snippets we have around the Det3 shop. While some are more globally useful such as the Flancter module and SDR SDRAM controller, most of these are targeted to the audio designer.
While we hope these snippets will be helpful to those who browse this page, we must place emphasis on the fact that you use this code at your own risk. Everything here is made available under a 4-clause BSD-Style license.
|Basic Flancter||The Flancter circuit was designed by Rob Weinstein, and is used for synchronizing signals crossing clock domains. The original publication was in Xilnx XCell journal #37, available here. This basic Flancter handles two clock domains, but care must be taken that the output flag is re-buffered for each domain to prevent metastable states from occurring.||flancter.tar.gz [TBA]|
|Simple SDR SDRAM Controller||This is a simple single-IC SDRAM controller. It handles all basic functions including initialization, refresh, and read/write operations to the SDRAM array. It is designed with an eye towards using an internal caching subsystem for building multiple audio delay lines used in effects processing.||d3-ssdram-1.0.tar.gz [TBA]|
|I2S TX/RX Modules||This snippet includes two modules which handle parallel audio to I2S data, and I2S data to parallel audio. It assumes that an appropriate audio clock is provided to the module and that everything in the system is locked to the clock. This allows a user to interface to standard audio ADCs and DACs.||d3-i2s-1.0.tar.gz [TBA]|
|Basic Interpolator||This basic interpolator provides both drop-sampling (nearest node picking) and linear interpolation for an external audio buffer. Please note that while pitch increments from 0 to well over 10 are supported, it is up to the user to take into account aliasing and harmonic distortion to achieve acceptable noise performance.||d3-linterp-1.0.tar.gz [TBA]|
|Delay Line AGU||This is a simple delay line address generator unit (AGU). It performs circular buffer arithmetic for handling multiple delay taps and modulation of each tap pointer. This allows the creation of multi-tap delays, phasers, flangers, and the like.||d3-dagu-1.0.tar.gz [TBA]|
|Biquad Filter||This is a basic biquad filter element. There are registers for each coefficient, and FPGA-specific multipliers are used to actually perform the filtering. Currently only Xilinx Spartan and Virtex multipliers are supported.||d3-biquad-1.0.tar.gz [TBA]|
|Simple audio DSP||This is a very simple audio DSP implementing 20 or 30 instructions, a MAC engine, circular buffer AGU (similar to the above module), and general-purpose ALU. There is a static memory interface and no support for external peripherals. Source code for the assembler and instruction map is provided. I hope this will teach the fundamentals of microprocessor design with a nod towards audio processing.||d3-adsp-1.0.tar.gz [TBA]|
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